1. Field of the Invention
The present invention relates to a memory device using a semiconductor.
2. Description of the Related Art
Terms used in this specification will be briefly explained. First, when one of a source and a drain of a transistor is called a drain, the other is called a source in this specification. That is, they are not distinguished depending on the potential level. Thus, a portion called a source in this specification can alternatively be referred to as a drain.
In this specification, “connection” means a structure in which effective direct current can be supplied at least temporarily. Therefore, a state of connection means not only a state of direct connection but also a state of indirect connection through a circuit element such as a wiring or a resistor, in which direct current can be supplied. It does not matter whether a circuit is actually designed so that direct current is supplied thereto.
For example, in the case where a switching element is provided between two nodes, direct current can be supplied in a certain condition (i.e., only when the switch is on); therefore, the structure can be expressed as “the nodes are connected to each other”. On the other hand, in the case where only a capacitor is provided between two nodes, effective direct current cannot be supplied through the capacitor; therefore, the structure can be expressed as “the nodes are not connected to each other”.
Similarly, in the case where only a diode is provided between nodes, direct current can be supplied when the potential of one of the nodes is higher; therefore, the structure can be expressed as “the nodes are connected to each other”. In this case, even if potentials with which current does not flow are supplied to the two nodes because of the circuit design (in which case current does not actually flow between the two nodes through the diode), the structure is expressed as “the nodes are connected to each other” in this specification.
For example, in the case where a node A is connected to a source of a transistor and a node B is connected to a drain of the transistor, direct current can flow between the node A and the node B depending on the potential of a gate; thus, the structure is expressed as “the node A and the node B are connected to each other”.
On the other hand, in the case where the node A is connected to the source of the transistor and a node C is connected to the gate of the transistor, effective direct current cannot flow between the node A and the node C regardless of the potentials of the source, drain, and gate of the transistor; thus, the structure is expressed as “the node A and the node C are not connected to each other”.
In the above description, effective direct current refers to current excluding unintentional current such as leakage current. Note that the value of effective direct current is not defined by its amount (absolute value) and sometimes depends on circuits. That is, in some cases, a low current of 1 pA can be effective current in one circuit, whereas a higher current of 1 μA is not considered as effective current in another circuit.
Needless to say, in one circuit having an input and an output (e.g., an inverter), the input and the output are not necessarily connected to each other. Using the inverter as an example, the input and the output are not connected to each other in the inverter.
When the term “connect” is used in this specification, there is a case in which a physical connection is not clear in an actual circuit and a wiring is only extended. For example, in a circuit composed of insulated-gate field-effect transistors (hereinafter simply referred to as transistors), one wiring serves as gates of a plurality of transistors in some cases. In this case, one wiring that branches into gates may be illustrated in a circuit diagram. In this specification, the expression “a wiring is connected to a gate” may be used even in such a case.
Further, in this specification, in referring to a specific row, column, or position in a matrix, a reference sign is accompanied by a sign denoting coordinates as follows, for example: “memory cell MC_1_1” and “bit line BL_2”. When one element has a function shared with a plurality of rows or columns, the element may be represented by, for example, “sense amplifier SA_1/2”.
On the other hand, when a row, column, or position of an element is not specified, when elements are collectively treated, or when the position of an element is obvious, the following expressions may be used, for example: “memory cell(s) MC” and “bit line(s) BL”, or simply “memory cell(s)” and “bit line(s)”.
A DRAM whose memory cell includes one transistor and one capacitor can be highly integrated, has no limit on the number of write cycles in principle, and can perform write and read operations at relatively high speed; thus, such a DRAM is used in many kinds of electronic devices. A DRAM stores data by accumulating electric charge in a capacitor of each memory cell, and reads the data by releasing the electric charge.
Several tens of refresh operations per second are conventionally required because silicon is used for a transistor, whereas a transistor including an oxide semiconductor, which has a wider bandgap, can store data substantially permanently (see Patent Document 1). In addition, the use of an extremely thin silicon film can reduce the off-state current of a transistor by three or more orders of magnitudes compared to a conventional one (see Patent Document 2).
FIGS. 2A and 2B illustrate a circuit and a method for reading data from a conventional DRAM. The DRAM illustrated in FIG. 2A is a folded bit line DRAM circuit and includes a pair of bit lines BL_1 and BL_2, word lines WL_1, WL_2, WL_3, WL_4, and the like, and memory cells MC_1_1, MC_2_2, MC_3_1, MC_4_2, and the like that are placed at the intersections of the bit lines and the word lines.
A sense amplifier SA_1/2 is provided at one end of the bit lines BL_1 and BL_2. The sense amplifier is usually a flip-flop circuit.
FIG. 2B is a timing chart for driving the memory cells and the sense amplifier. Here, a capacitor in the memory cell MC is charged with +1 V as one-bit data representing “1” and charged with 0 V as one-bit data representing “0”.
Data in the memory cell MC_1_1 is read in the following manner. First, the bit lines BL_1 and BL_2 are precharged with +0.5 V by a precharge circuit (not illustrated). Then, the bit lines BL_1 and BL_2 are brought into a floating state. Here, in the flip-flop sense amplifier SA_1/2, a wiring VPS for supplying its potential to sources of p-channel transistors TPU and TPD and a wiring VNS for supplying its potential to sources of n-channel transistors TNU and TND have a potential of +0.5 V.
After that, the potential of the word line WL_1 is set at an appropriate value to turn on the cell transistor in the memory cell MC_1_1 (time T1 in FIG. 2B). Note that the operation “changing a potential of a wiring to turn on a transistor connected to the wiring” is referred to as setting the potential of the wiring at the ON potential. By this operation, electric charge stored in the capacitor in the memory cell MC_1_1 is discharged to the bit line BL_1.
The potential of the bit line BL_1 is determined by the capacitance of the capacitor in the memory cell MC_1_1 and the capacitance of the bit line BL_1. Here, since the potential of the capacitor in the memory cell is originally 0 V, the potential of the bit line BL_1 falls from the precharge potential to +0.4 V, for example.
On the other hand, the potential of the bit line BL_2 does not change and remains at +0.5 V even when the potential of the word line WL_1 is set at the ON potential, because there is no memory cell connected to the bit line BL_2. That is, the potential of the bit line BL_1 is lower than that of the bit line BL_2 by 0.1 V.
Then, the potential of the wiring VPS of the sense amplifier SA_1/2 starts to be raised to +1 V at a given speed, and the potential of the wiring VNS starts to be lowered to 0 V at a similar speed (time T2 in FIG. 2B). Accordingly, the p-channel transistor TPD and the n-channel transistor TNU are turned on at a given moment.
Consequently, the potential of the bit line BL_1, which is relatively low, is further lowered and the potential of the bit line BL_2, which is relatively high, is further raised, and in the end, the potential of the bit line BL_1 becomes 0 V and the potential of the bit line BL_2 becomes +1 V.
It is preferable that the speed of change in the potential of the wiring VPS and the potential of the wiring VNS be sufficiently low at an early stage of the amplification process. This is because, when the potential difference at an early stage of the amplification is as small as 0.1 V as described above, amplification fails if the potential of the wiring VPS and the potential of the wiring VNS are rapidly changed. For that reason, the amplification requires time.
In contrast, if it takes long time to complete the amplification, the possibility of reading failure due to external noise increases particularly at an early stage of the amplification.
The threshold voltage variation of the transistors included in the sense amplifier SA_1/2 is required to be small because the sense amplifier SA_1/2 amplifies a potential difference as small as 0.1 V. Given that, for example, the threshold voltages of the n-channel transistor TNU, the p-channel transistor TPU, the n-channel transistor TND, and the p-channel transistor TPD are +0.35 V, −0.45 V, +0.45 V, and −0.35V, respectively, both the p-channel transistor TPU and the p-channel transistor TPD are turned on in the amplification process and data reading fails in some cases.
In general, the threshold voltage variation of the transistors included in a sense amplifier needs to be less than half, preferably less than 30% of the potential difference between bit lines at an early stage of amplification. In the above case, an error is likely to occur at the time of amplification since the threshold voltage variation of the transistors is 50 mV and the potential difference between the bit lines at an early stage of the amplification is 0.1 V.
In general, the threshold voltage variation of transistors is broadly classified into three types: lot-to-lot variation (substrate-to-substrate variation), chip-to-chip variation (variation within one substrate), and variation between adjacent transistors.
Lot-to-lot variation depends on difference in process condition, film thickness, and line width between lots. Chip-to-chip variation is due to variation in dose, film thickness, and line width within one substrate. Either variation is macroscopic variation, and threshold voltage variation caused by these factors can be corrected by substrate bias, for example.
On the other hand, variation between adjacent transistors is mainly due to statistical fluctuations in dopant concentration (see Non-Patent Document 1) and increases as the transistors are reduced in size. In other words, the reduction in size of transistors for high integration of DRAM makes the operation of a sense amplifier unstable.
In the case of using a semiconductor whose mobility is lower than that of silicon by one or more orders of magnitude, such as an oxide semiconductor, the capacitance of a capacitor needs to be lower than that of an ordinal capacitor by one or more orders of magnitude in order to access data at high speed. If the number of memory cells connected to one bit line is equivalent to that in a conventional DRAM, the change in the potential of the bit line at the time of data reading becomes smaller and thus an error is likely to occur.
According to Non-Patent Document 2, when the number of memory cells connected to a bit line is 256, the capacitance of the bit line is 35 fF with a circuit line width of 40 nm. If 256 memory cells are connected to one bit line while the capacitance of a capacitor is 3 fF, the change in the potential of the bit line is approximately 40 mV; thus, a technique of amplifying such a small potential change in a short time without errors is required.